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| Vendor: | Mentor Graphics Corp | Tool Website | TestKompress |
| Suite: | Design Level:IC Level DFT | Discipline:Automatic Test Vector Generation | Domain:Electrical |
| Tool Function: | embedded compression logic generation, automatic test pattern generation, 100x compression of scan test patterns with as few as one scan channel, test coverage analysis. | ||
| Tool Inputs: | compression logic generation with: - fundamental scan definition or gate netlist ATPG with - gate level netlist, - dft library. |
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| Tool Outputs: |
compression logic generation: - RTL compression logic - synthesis scripts - coverage and compression estimates - setup for atpg ATPG - simulation patterns (verilog) - ATE patterns (STIL, WGL, or custom) - coverage analysis |
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| Associated Tools: | interfaces to most testers and time based simulators. - Calibre physical tools for layout-aware ATPG such as bridge patterns - SDF for timing-aware ATPG - SDC for false and multicycle path definitions during at-speed ATPG |
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| Tool Cost Range: Over $100,000 | Licensing Term: Perpetual License | Tool Licensing Mechanism:flexible configurations available (node-locked, server based, floating, site licence, etc.) | How long has tool been available: Over 5 years |
| Training: | On-site and at training facilities. | ||
| Contact: | Ron Press | ||